Nonvolatile semiconductor memory devices often achieve nonvolatility (i.e., the ability to store data in absence of an applied power supply voltage) by the use of a charge storage mechanism. For example, charge may be stored in a "floating" gate (a conductive element surrounded by a dielectric) or at a dielectric interface, such as a silicon dioxide/silicon nitride interface.
In order to utilize charge storage mechanisms, an electric field must be generated to transport the charge from a source location to a destination location. An example of one type of mechanism is set forth in FIGS. 1, 2A and 2B. FIG. 1 sets forth a side cross sectional view of a nonvolatile memory device of a type that may be used in an electrically programmable read only memory (EPROM) or an electrically erasable and programmable memory (EEPROM). The memory device is a so-called "one-transistor" (1-T) memory cell, and is designated by the general reference character 100. The memory cell 100 is shown to be formed in a p-type semiconductor substrate 102, and includes an n-type source region 104 and f-type drain region 106, separated by a channel region 108. A floating gate 110 and a control gate 112 are formed over the channel region 108. The floating gate 110 is separated from the substrate 102 by a first dielectric 114, which may be a tunnel dielectric in the case of an EEPROM. The floating gate 112 is separated from the control gate 112 by a second dielectric 116.
The prior art 1-T cell 100 is programmed by placing electrons on the floating gate 110 by the charge transport mechanism known as hot electron injection. A first field is created by placing the source region 104 at a low potential (Vss) and the drain region 106 at a high potential (Vp). This first field accelerates electrons from the source region 104 into the channel 108. A second field across the floating gate 110, created by capacitive coupling, is generated by applying a very high potential (Vpp) to the control gate 116. As the first field accelerates the electrons into the channel 108, they are attracted toward the floating gate 110 by the second field, and then trapped in the floating gate 110. A symbolic representation of an electron being accelerated from the source region 104, across the channel 108, and into the floating gate 110 is set forth in FIG. 1.
The 1-T cell 100 essentially functions as an insulated gate field effect transistor (IGFET), with the threshold voltage being altered by the amount of charge that is stored in the floating gate 110.
FIG. 2A is a block schematic diagram illustrating a portion of a nonvolatile memory device 200, including those structures necessary for applying the high drain voltage Vp, required in a programming operation. The memory device 200 includes four 1-T cells 202a-202d, arranged in two rows and two columns. Cells within the same column are commonly coupled to a bit line 204a and 204b. Cells within the same row are commonly coupled to a row line 206a and 206b. The bit lines 204a and 204b are coupled to a drain programming voltage (Vp) source 208 by a column selector 210. In operation, SELECT signals are applied to the column selector 210, and in response thereto, the column selector 210 couples the voltage Vp to selected bit lines, and consequently, to the drains of those memory cells coupled to the selected bit lines. It is understood that at the same time the voltage Vp is applied to the drains of the selected memory cells, the gates of the memory cells within a selected row are driven to the very high Vpp voltage. The sources of the memory cells are maintained at the low voltage Vss.
FIG. 2B provides a more detailed schematic diagram illustrating the application of the voltage Vp to the drain of one memory cell. A memory cell 202 is represented by a typical 1-T cell symbol Q200. In addition, a diode D200 is shown in parallel with the 1-T symbol. The diode represents the p-n junction created by the n-type source region formed within the p-type substrate. The drain of the memory cell 202 (the cathode of diode D200) is coupled to the Vp voltage source by the column selector 210, which includes three n-channel metal-oxide-semiconductor (MOS) transistors (N200, N201 and N202) connected in series. Transistors N201 and N202 are driven by column select signals Yse1 and Zse1, which can be generated from address decoder circuits. Transistor N200 is driven by a DATA signal, representative of the data that is to be written into the memory cell 202. For example, if a logic "0" is to be written into the memory cell 202 the DATA signal would be high, and the memory cell 202 would be programmed. If a logic "1" is to be written, the DATA signal would be low, and the memory cell 202 would not be programmed.
A drawback to the programming arrangement set forth in FIGS. 1, 2A and 2B is the possibility that the drain voltage may exceed the reverse breakdown voltage of the drain-source diode. A reverse breakdown condition at the drain p-n junction can give rise to a number of undesirable effects. The breakdown of the p-n junction can lead to the generation of high-energy "hot" holes. These hot holes can be injected into the oxide that separates the substrate from the floating gate. Such trapped hot holes have been attributed to contributing in the breakdown of the oxide, resulting in higher leakage current and/or decreased reliability in the memory cell operation. In addition, it is believed that such trapped holes can subsequently migrate to the floating gate 110/oxide 114 interface and cancel the effect of electrons stored in the floating gate 110. The threshold voltage of a programmed cell can be lowered.
The reverse breakdown of the drain diode also impacts the controllability of programming. With the breakdown of the junction, the carrier generation mechanism becomes dominated by band to band tunneling, instead of hot carriers. As a result, the ability to control the amount of charge that is stored within the floating gate may be impacted, adversely affecting the resulting threshold voltage of the nonvolatile storage device.
The breakdown of the p-n junction in a nonvolatile memory cell may also occur in the erase operation of an EEPROM cell. Referring now to FIG. 3, a 1-T EEPROM cell is set forth in a side cross sectional view, and designated by the general reference character 300. As in the case of the memory cell 200 set forth in FIG. 1, the 1-T EEPROM cell 300 is formed in a p-type semiconductor substrate 302, has an n-type source region 304 and an n-type drain region 306 separated by a channel 308. A floating gate 310 and control gate 312 is formed above the channel 308. The first dielectric of the memory cell 300 is a tunnel dielectric 314; the second dielectric 316 is an intergate dielectric.
In the particular example set forth in FIG. 3, the erasure of the cell is accomplished by tunneling electrons stored on the floating gate 310 to the source region 304. A relatively large negative gate erase voltage (-Vge) is applied to the control gate 312, the source region 304 receives a positive voltage Vse, and the drain region 306 is placed into a floating (high impedance) state. Due to the relatively large negative voltage (-Vge) at the control gate 312, and the positive voltage (Vse) at the source regions 304, an electric field is created between the floating gate 310 and the source region 304 causing electrons to tunnel from the floating gate 310 through the tunnel dielectric 314 to the source region 304.
FIG. 4A is block diagram illustrating the application of the source erase voltage Vse to the sources of the memory cells in an EEPROM. The portion of the EEPROM is designated by the reference character 400 and has many of the same elements as the EEPROM in FIG. 2A, including four, 1-T memory cells 402a-402d, two bit lines 404a and 404b , and two word lines 406a and 406b. In the particular embodiment of FIG. 4A the sources of the memory cells (402a-402d) are commonly coupled to a source erase voltage Vse 410, by a source selector 412. A detailed schematic diagram in FIG. 4B illustrates the application of the voltage Vse to one memory cell 402. The Vse voltage is generated in the Vse source 410, and applied to the source of the memory cell 402 by a source selector 412 that includes a complementary MOS (CMOS) driver, composed of p-channel MOS transistor P400 and n-channel MOS transistor N400. During an erase operation, a SELECT signal at the gates of transistors P400 and N400 goes low, applying the Vse voltage to the source of the memory cell 402. The memory cell 402 is represented by 1-T cell symbol Q400, with the p-n junction created by the source regions being represented by a diode D400.
As in the case of the programming operation described above, it is desirable to avoid the reverse breakdown of the source-substrate p-n junction during an erase operation, as this leads to the generation hot holes, and the adverse consequences thereof.
It would be desirable to reduce the adverse effects of junction breakdown during the programming and erase operation of nonvolatile memory cells.